All MCQs Tests - VU CS302 - Digital Logic Design

Question 1: The CONSTATE.CLK = Clock is used to indicate that the __________ state variables change on a clock transition.

Question 2: A frequency counter __________

Question 3: The outputs of SR latches in elevator state machine are feed back to the __________ gate array for connection to the D-flipflops.

Question 4: A 8-bit serial in / parallel out shift register contains the value "8", __________ clock signal(s) will be required to shift the value completely out of the register.

Question 5: Excess-8 code assigns __________ to "+7"

Question 6: In __________ the Q output of the lasy flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register.

Question 7: In case of cascading Integrated Circuit counters, the enable inputs and RCO of the Integrated Circuit counters allow cascading of multiple counters together.

Question 8: The low to high or high to low transition of the considered to be a __________

Question 9: Demorgan's two theorems prove the equivalency of the NAND and __________ gates and the NOR and __________ gates respectively.

Question 10: Addition of two octal numbers "36" and "71" results in __________